Conventionally, a gate driver (a scanning signal line drive circuit) for driving gate lines (scanning signal lines) of a liquid crystal display device is often mounted as an IC (Integrated Circuit) chip in a peripheral portion of a substrate serving as a component of a liquid crystal panel. In recent years, however, formation of a gate driver directly formed on a substrate is gradually increasing. Such a gate driver is called a “monolithic gate driver” or the like.
In a liquid crystal display device having a monolithic gate driver, a thin film transistor using amorphous silicon (a-Si) (hereinbelow, called an “a-Si TFT”) is employed conventionally as a drive element. However, in recent years, a thin film transistor using microcrystalline silicon (μc-Si) (hereinbelow, called a “μc-Si TFT”) or a thin film transistor using an oxide semiconductor (for example, IGZO) is being adopted as a drive element. Hereinafter, a thin film transistor using IGZO will be called an “IGZO TFT”. The μc-Si TFT and IGZO TFT have mobility higher than that of a-Si TFT. Consequently, by adopting μc-Si TFT or IGZO TFT as a drive element, reduction in a picture-frame area of the liquid crystal display device and higher definition can be realized.
A display unit in an active matrix-type liquid crystal display device includes a plurality of source lines (video signal lines), a plurality of gate lines, and a plurality of pixel formation portions provided in correspondence with intersecting points of the plurality of source lines and the plurality of gate lines. The pixel formation portions are arranged in a matrix, thereby constituting a pixel array. Each of the pixel formation portions includes a thin film transistor (switching element) having a gate terminal connected to a gate line passing a corresponding intersecting point and a source terminal connected to a source line passing the intersecting point, a pixel capacitance for holding pixel voltage, and so on. The active matrix-type liquid crystal display device is also provided with the above-described gate driver and a source driver (video signal line drive circuit) for driving source lines.
A video signal indicative of a pixel voltage value is transmitted through a source line. However, video signals indicative of pixel voltage values for a plurality of rows cannot be transmitted by each source line at once (simultaneously). Due to this, the video signals are sequentially written (charged) line by line to the pixel capacitances in the above-described pixel formation portions arranged in a matrix. Consequently, the gate driver is configured by a shift register including a plurality of stages so that the plurality of gate lines are sequentially selected by predetermined periods. Each of the stages of the shift register is a bistable circuit which is in either one of two states (a first state and a second state) at each time point and outputs a signal indicative of the state (hereinbelow, called a “state signal”) as a scanning signal. By outputting active scanning signals sequentially from a plurality of bistable circuits in the shift register, the video signals are sequentially written to the pixel capacitances line by line as described above.
Such a bistable circuit is configured by an element such as the above-described a-Si TFT, μc-Si TFT, or IGZO TFT. It is, however, generally known that a threshold value shifts with operation time as to those transistors. FIG. 16 is an Id-Vgs characteristic diagram of an n-channel-type transistor. It should be noted that Id expresses a drain current, and Vgs expresses a gate-source voltage. The solid line in the diagram expresses the characteristic before threshold shift, and the broken line expresses the characteristic after threshold shift. As illustrated in FIG. 16, the threshold shifts to the positive direction with the operation time. Particularly, when threshold shift occurs in a transistor regulating output of a scanning signal, the scanning signal becomes dull as illustrated in FIG. 17. It should be noted that the solid line in the diagram expresses a scanning signal before the threshold shift, and the broken line expresses a scanning signal after the threshold shift.
In relation to the present invention, Patent Document 1 discloses a shift register in which, as illustrated in FIG. 18, each stage is configured by a pull-up unit 171, a pull-down unit 172, a pull-up driving unit 173, a first pull-down driving unit 174, and a second pull-down driving unit 175. The pull-up unit 171 is configured by a transistor M1. The pull-down unit 172 is configured by a transistor M2. The pull-up driving unit 173 is configured by a capacitor C and transistors M3 to M5. The first pull-down driving unit 174 is configured by transistors M6 and M7 as a first inverter. The second pull-down driving unit 175 is configured by transistors M8 and M9 as a second inverter for controlling the first inverter. An output of the second pull-down driving unit 175 is supplied to a gate terminal of the transistor M6 connected to a VON side in the first pull-down driving unit 174. With such a configuration, the difference in the channel width between the transistors M6 and M7 in the first pull-down driving unit 174 can be minimized, so that the flow of an excessive current to the transistor M6 can be prevented. Consequently, deterioration in the transistor M6 can be prevented.